1. Field of the Invention
The present invention relates to semiconductor package substrates having contact pad protective layers formed thereon and methods for fabricating the same, and more particularly, to a semiconductor package substrate having a contact pad protective layer formed thereon and a method for fabricating the same, such that a metal protective layer is formed on the contact pad of the substrate while the substrate circuit and conductive vias are fabricated.
2. Description of the Related Art
In the trend to develop an electrical device that is compact, multi-functional, and operated at high speed and high frequency, technology in Printed Circuit Board (PCB) and Integrated Circuit (IC) package substrate has been directed to develop the electrical device with thinner circuit and smaller apertures. The circuit dimensions including line width, trace space, and aspect ratio have been reduced from 100 μm and above in the conventional process to 30 μm in current fabrication process for PCB or IC package substrate. And research for developing the device with smaller circuit precision is now underway.
Typically, a conventional etching method incurring with lower cost and less etching time is usually adopted when the dimension of conductive trace is above 40 μm. Referring to FIGS. 1A and 1B, a metal layer 11 is formed on an insulating layer 10, followed by coating a resist layer 12 on the metal layer 11. Next, in a wet etching method, a strong acid or alkaline etchant 13 has diffused to react with surface molecules of the metal layer 11 to complete the removal by etching. Besides having a higher etching rate and lower cost, such subtractive etching method is also beneficial in terms of higher thickness uniformity for conductive layer after etching. As the etching is achieved through a chemical reaction between the etchant 13 and the specific materials, it has a better etching selectivity than other methods. So, other materials not to be etched are not removed. Since the wet etching method is an isotropic etching, an undercut 14 results as shown in FIG. 1B to affect the process precision when a downward etching is performed. Such wet etching method is limited in precision of mass transport, making the conductive trace to be etched harder to be developed into smaller dimension.
For the dry etching method that is commonly adopted in the semiconductor process, an anisotropic etching characteristics thereof may lead to a finer etching precision and smaller line width for the conductive trace, regardless of sputtering etching or plasma etching. However, such dry etching method with a low etching rate (a few nanometers for each minute) is only suitable for the thinner semiconductor chip, but not for the thicker package substrate (5 to 30 μm) as more time and cost are spent to perform dry etching in this case. Meanwhile, the dry etching method is a physical etching method that bombards the etching surface with ions and has poor etching selectivity. So, if the dry etching method is adopted in the entire process for fabricating the package substrate, the conductive layer may have been polluted.
Instead of the conventional subtractive etching method, an additive etching method is currently adopted for fabricating finer circuits in the industry to fulfill requirement for circuit board of higher density. Conventionally, this method is achieved by forming a seed layer with electroless copper on the insulating circuit board, followed by forming a circuit layer directly above the insulating layer to prevent problems encountered during etching. The method is sub-divided into a fully additive process and a semi-additive process.
A typical semi-additive process for fabricating a finer circuit is illustrated in FIGS. 2A through to 2F.
Referring to FIG. 2A, a core circuit board 20 has a plurality of patterned circuit layers 21, an insulating layer 22 located between two circuit layers 21, and a plated through hole (PTH) 23 for interconnecting the circuit layers 21.
As shown in FIG. 2B, two organic insulating layers 24 are further mounted by vacuum compression on surfaces of the core circuit board 20.
Referring to FIG. 2C, the organic insulating layers 24 are patterned to form a plurality of openings 240 for exposing parts of the circuit layer 21. An electroless copper film 25 is formed on each of the organic insulating layers 24 and covers the openings 240.
Referring to FIG. 2D, a patterned resist layer 26 is formed on the electroless copper film 25 such that a plurality of openings 260 are formed in the patterned resist layer 26 to expose parts of the electroless copper film 25.
Referring to FIG. 2E, a trace layer 27 is formed in the opening by electroplating, wherein the electroplated metal layer is generally a conductive trace made of copper.
Referring to FIG. 2F, a four layers stacked substrate 200 is formed after the resist layer 26 and parts of the electroless copper film 25 covered by the resist layer 26 are removed.
A plurality of conductive traces made of copper are formed on a surface of the semiconductor package substrate, with parts of the surface form contact pads for transmitting electrical signals or power. A metal layer, such as nickel (Ni)/gold (Au) layer is commonly formed on exposed surface of the contact pads to provide the contact pads with such as Au wires, bumps or solder balls for an effective electrical coupling to conductive devices such as chips or circuit boards. Thus, the contact pads are prevented from being oxidized by the external environment.
The contact pads may be the bump pads or presolder pads for coupling electrically the flip chip package substrate to the chip. The contact pads may also be fingers for coupling electrically the wire-bonded package substrate to the chip or ball pads for coupling electrically the package substrate to the circuit board. A Ni/Au metal layer is formed on exposed surface of the contact pads to protect the contact pads (usually copper (Cu)) from being oxidized by external environment, so as to improve connection for the bumps, presolders, or solder balls mounted on the contact pads.
Since the electroless copper film used for entire connection in the current semi-additive process (SAP) is removed by etching after the pattern plating process, a process for forming a solder masking agent (i.e. green paint) is performed on the substrate to protect the electroplated trace layer from being oxidized. And openings are formed in the solder mask to expose the surfaces of the contact pads for forming the Ni/Cu metal layer. As the electroless copper film has been removed, the formation of the Ni/Au metal layer has to be carried out by an electroless method, i.e. adopting a driving force without application of external voltage.
FIGS. 2G through to 2H illustrate a conventional electroless method for forming the metal barrier layer on contact pads of the substrate, i.e. formation of nickel (Ni)/gold (Au) metal layer by a chemical deposition process.
Referring to FIG. 2G, as described above, a substrate 200 which is formed with a patterned circuit layer 27 in the front-end process, is printed or coated with a solder mask, such as a green paint. The circuit layer 27 comprises a plurality of contact pads 270 that are exposed by openings 280 formed in the solder mask 28, in order to correctly deposit the Ni/Au metal layer on the contact pads.
Referring to FIG. 2H, during the chemical deposition process, the substrate 200 is subjected to an Electroless Nickel/Immersion Gold (EN/IG) process, where a Ni/Au metal layer 29 is deposited via the openings 280 on surfaces of the contact pads 270 exposed by the openings 280.
Thus, as described above, the electroless copper film for interconnecting the electroplated patterned traces in the SAP is removed after the trace patterning, the Ni/Au metal layer is subsequently formed in an electroless method. The typical liquid adopted in the conventional chemical deposition method usually results a corrosive attack to the solder mask formed on the package substrate, causing peeling of the solder mask and poor reliability as a result of pollution for the Ni/Au metal layer on the contact pads.
And to meet the market demand, semiconductor manufacturers are eagerly involved in developing the semiconductor package with a more compact size as well as the chip of smaller size and higher integration. So, the semiconductor package substrate that serves as a chip carrier is formed with contact pads in high density, so that the chip carried on the substrate forms an excellent and complete connection with the substrate, and the highly integrated chip operates smoothly to develop its functions and properties. However, as the IC package substrate formed with the conductive traces is limited in terms of its fabrication process, limitations in the transmission chip signal and functions to improve bandwidth and control resistance thereof deters development in a high input/output (I/O) package. As the IC process width has been reduced down to 0.13 μm for the semiconductor chip, the package size is also constantly reduced until it almost reaches the same size of the chip (about 1.2 times the size of the chip). Therefore, development in the package substrate with fine circuit, high density, and small apertures is in no doubt an important research topic for IC industry and other related electronic industries to advance to the technology of next generation since the substrate process occupies 20% to 50% of the package cost.
And if the conductive trace is developed to achieve a higher precision, dimensions of the contact pad as well as a pitch between two neighboring contact pads need to be further reduced. As a result, the openings that form in the solder mask become too small to expose the contact pads, causing poor fluid convection in the chemical Ni/Au deposition process, and further leading to poor mass transfer for the Ni particles without full Ni plating. So, the Ni metal layer is not successfully plated by immersing in deposited Au, resulting either a skip in electroplating or a surface of the contact pad which is too rough to form a dense Ni/Au metal layer.